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MX25L4004
4M-BIT [4M x 1] CMOS SERIAL FLASH EEPROM
FEATURES
* Low voltage operation: 2.7V ~ 3.6V * SPI Bus compatible * Sector erase architecture: - 1024 equal sectors of 536 bytes each - Sector erase time: 8ms typical * Page program operation: - Internal data latches for 134 bytes per page - Page programming time: 3ms typical * Auto Erase and Auto Program algorithms: - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page * Four independently protected sectors on the top for boot code storage * Status register feature for detection of - Program or erase cycle completion - Array to Buffer transfer - Sleep - Auto Program/Erase error report * Six extra bytes on each page for user page management * Dual buffers for buffer write when chip is busy * Input data format: - 1-byte OP code, 2-byte sector address, 1-byte page number, 1-byte byte address * 32-pin TSOP TYPE(I)
GENERAL DESCRIPTION
The MX25L4004 is a CMOS 4,390,912 bit serial Flash EEPROM, which is configured as 548,864 x 8 internally. The MX25L4004 features a serial peripheral interface and software protocal allowing operation on a simple 3- wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS input. The MX25L4004 features sector protected and unprotected modes, which disable/enable both program and erase operation in the top four sectors. After program/erase command is issued, auto program/ erase algorithms which program/erase and verify the specified sector/page locations will be executed. Program command is executed on a page (134 bytes) basis, and erase command is executed on a sector (536 bytes) basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion and error flag status of a program or erase operation. When the device is not in operation and CS is high, it is put in standby mode and draws less than 30uA DC current. To save power further, the device may be put into sleep mode. During sleep mode, the device only draws 1uA DC current. Recovery time from sleep mode is less than 25us. The MX25L4004 utilizes MXIC's proprietary memory cell which reliably stores memory contents even after 10,000 program and erase cycles.
P/N: PM0305
REV. 2.7, SEP 14,1998
1
INDEX
MX25L4004
PIN CONFIGURATIONS
SCLK SO VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PIN DESCRIPTION
TEST PROT
SYMBOL CS TEST SI SO SCLK PROT VCC VSS All other pins
DESCRIPTION Chip Select Test Mode Select Serial Data Input Serial Data Output Clock Input Protection Enable + 3.0V Power Supply Ground Not Connected
32 TSOP(I)
CS SI VSS
Note: 1.TEST input is used for in-house tesing and must be tied to ground during normal user operation.
BLOCK DIAGRAM
Address Generator
X-Decoder
Memory Array (2144 x 2048)
Secondary Buffer Primary Buffer DI Data Register Y-Decoder
CS PROT
Mode Logic
State Machine
Sense Amplifier HV Generator
Output Buffer
SO SCLK Clock Generator
P/N: PM0305
2
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
COMMAND DEFINITION
Command 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Action Read Array 52H SA2 SA1 PN BA X X X X n bytes read out until CS Array to Buffer 53H SA2 SA1 PN Read Buffer 81H BA X Write Buffer 82H BA Status Read 83H Clear Status 89H Read ID 85H X Read Error Buffer 86H X
start to transfer at CS
n bytes read out until CS
n bytes write until CS
Output status byte until CS Wake Up 87H
Clear status byte
Output vendor code until CS
n bytes read out until CS
Command 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte Action
Sector Erase F1H SA2 SA1
Page Program F2H SA2 SA1 PN BA
Extra Byte Program F3H SA2 SA1 PN BA
Sleep
88H
Start to erase at CS
Load n bytes data to buffer until CS & start to program
Load n bytes data to extra byte buffer until CS & start to program
Enter sleep mode
Enter standby mode
Sleep bit set
Sleep bit reset
1-byte op code Bit7(MSB), Bit6, Bit5, Bit4, Bit3, Bit2, Bit1, Bit0 2-byte sector address(0 to 03FFH) SA1: A17 A16 A15 A14 A13 A12 A11 SA2: X X X X X X A19 1-byte page number(0 to 3) PN: X X X X X X A9 1-byte page address(0 to 85H) BA: A7 A6 A5 A4 A3 A2 A1 A7 = 0 -------> 128 normal bytes A7 = 1 -------> 6 extra bytes
P/N: PM0305
A10 A18 A8 A0
3
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
DEVICE OPERATION(please refer to serial data input/output timing on page 10 for basic bus timing)
Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
COMMAND DESCRIPTION (1) Read Array
This command is sent with the sector address, the page number, and the byte address, followed by four dummy bytes sent to give the device time to stabilize. The device will then send out data starting at the byte address until CS goes high. The clock to clock out the data is supplied by the master SPI. If the end of the page is reached then the device will wrap around to the beginning of the page.
(2) Array to Buffer
This command is sent with the sector address and the page number. The device will then transfer the entire page into the page buffer without any further input. This should be completed in under 40 s.
(3) Read Buffer
This command is sent with the byte address, followed by a dummy byte. The device will then send out the data starting at the byte address until CS goes high. The clock to clock out the data is supplied by the master SPI. If the end of the page is reached then the device will wrap around to the beginning of the page.
(4) Write Buffer
This command is sent with the byte address. The device will then receive the data starting at the byte address until CS goes high. The clock to clock in the data is supplied by the master SPI. If the end of the page is reached then the device will wrap around to the beginning of the page. The write buffer command could be issued after 40s from the rising edge of CS of program/erase operation.
(5) Read Status Register
When this command is sent, the device will continuously send out the status register contents starting at bit7. The clock to clock out the data is supplied by the master SPI. bit7 ready busy 1=busy bit6 array to buf 1=transfering bit5 sleep 1=sleep bit4 erase error 1=error bit3 program error 1=error bit2 bit1 bit0
0
0
0
Bit 7 = "1" -----> Device is busy doing program /erase operation. = "0" -----> Device is not doing program/erase operation. Bit 6 = "1" -----> Device is busy doing array to buffer transfer. = "0" -----> Device is not doing array to buffer transfer.
P/N: PM0305
4
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
Bit 5 = "1" -----> Device is in sleep mode. = "0" -----> Device is not in sleep mode. Bit 4 = "1" -----> There is an error occurred in last erase operation. = "0" -----> There is no error occurred in last erase operation. Bit 3 = "1" -----> There is an error occurred in last program operation. Error location could be extracted in read error buffer mode. = "0" -----> There is no error occurred in last program operation. (6) Clear Status Register This command only resets erase error bit (bit 4) and program error bit (bit 3) . These two bits are set by on-chip state machine during program/erase operation, and can only be reset by issuing a clear status register command or by powering down VCC . For other bits of the status register, R/B bit (bit 7) wil be automatically reset when device completes program/rease operation, array to buffer bit (bit 6) is reset when array to buffer transfer is completed, and sleep bit (bit 5) is automatically reset when device gets out of sleep mode. If status register indicates that error occured in the last program/erase operation, any further program/erase operation will be prohibited until status register is cleared.
(7) Read ID This command is sent with an extra dummy byte( a 2-byte command). The device will clock out manfacturer code (C2H) and device code (42H) when this command is issued. The clock to clock out the data is supplied by the master SPI.
(8) Read Error Buffer This command is sent with a dummy byte. If the error flag is set after programming, read error buffer command can be issued to find the failed location(s). This command will cycle through the whole page and clock out the data of error buffer sequentially from byte 0 until CS goes high, so the error(s) can be determined and appropriate action taken. This will be accomplished without disturbing the contents of the primary buffer. Any "0" in the output string means error at the corresponding location. Status register will be cleared automatically when this command is issued. (9) Sector Erase This command is sent with the sector address. The device will start the erase sequence after CS goes high without any further input. A sector should be erased in a typical of 8ms. The write buffer command can be issued in preparation for the next programming sequence after 40us from the rising edge of CS of the current erase operation. The average current is less than 25mA.
(10) Page Program This command is sent with the sector address, page number, and byte address, followed by programming data. One to 134 bytes(including extra bytes) of data can be loaded into the device and then simultaneously written during the programming period. Until CS goes high the device will program the specified page with buffered data. The typical page program time is 3ms. The write buffer command can be issued in preparation for the next programming sequence after 40s from the rising edge of CS of the current program operation. The average current is less than 25mA.
P/N: PM0305
5
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
(11) Extra Byte Program This command is sent with sector address, page number, and byte address, followed by programming data. Only extra bytes will be simultaneously written during the programming period. Until CS goes high the device will program the specified page address with buffered data. The typical extra byte page program time is 3ms. The Write Buffer command can be issued in preparation for the next programming sequence after 40us from the rising edge of CS of the on-going program operation. The average current is less than 25mA. Please note that only extra bytes (from page address 80H to 85H) will be programmed by issuing this command. Extra byte program provides users with the convenience of programming extra bytes without having to load data for regular bytes. The error buffer would be cleared if this command is issued. (12) Sleep The Sleep command can be issued during Array to Buffer, Sector Erase, or Page Program operation before completion, or in standby mode. Once current operation is completed, either Ready/Busy bit (bit7) or Array to Buffer bit (bit 6)is reset, and Sleep bit is set. Since status register is not reset during sleep mode, error bit (bit4 or bit 3) may have been set in the last erase or program operation. Issuing a wake up command will bring the device out of the sleep mode. The read status register command could be issued to detect the status bit. Typical sleep current is less than 1uA. (13) Wake up This command will bring the device out of the sleep mode and prepare it for the next operation. The next command should be issued at less 25us later.
OTHER OPERATION MODES
(1)Standby Mode When CS is high and there is no operation in progress, the device is put in standby mode. Typical standby current is less than 30uA. (2)Write Protect Mode If PROT pin is sampled high on falling edge of CS input, the top 4 sectors will be protected from Program or Erase operation; please refer to the PROT signal timing on page 10. Other sectors are not subject to this protection mechanism.
POWER-ON STATE
After power-up, the device is placed in the following state : * The status register is reset. Bit 7 = "0" -----> Device is not in program/erase operation. Bit 6 = "0" -----> Device is not in array to buffer mode. Bit 5 = "0" -----> Device is not in sleep state. Bit 4 = "0" -----> Erase error flag is reset. Bit 3 = "0" -----> Program error flag is reset.
DATA SEQUENCE
Output data is serially sent out through SO pin, synchronized with the falling edge of SCLK, whereas input data is serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data is bit 7 (MSB) first, then bit 6, bit 5, ...., and bit 0.
P/N: PM0305
6
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
ADDRESS SEQUENCE
The address assignment is described as follows : BA : byte address, used to specify byte location within a page. Bit sequence: A7 A6 A5 A4 A3 A2 A1 A0 A7 = 0 to select regular byte A7 = 1 to select extra byte PN : page number, used to select a page within a sector Bit sequence: X X X X X X A9 A8 SA1, SA2 : sector address, used to select a sector. SA1 Bit sequence: A17 A16 A15 A14 A13 A12 A11 A10 SA2 Bit sequence: X X X X X X A19 A18
APPLICATION EXAMPLE
PAGE PROGRAM FLOW CHART This example demonstrates how errors detected in the current page can be corrected immediately after page program operation. Only 6 bytes of host memory is needed temporarily save data for 6 extra bytes. Extra bytes provides users with a method to record the errors occured in the normal 128 bytes.
DEFECT MANAGMENT FOR PAGE PROGRAM
m=m+1 START m=0
Page Program Page m
Read Status
PGM Done ?
NO
Read Error Buffer PGM Error ? YES EX-BYTE PGM pg m ex-byte
NO
NO
Last Page ?
Read Status
YES Stop PGM Done ? YES NO
PGN Error ?
YES
Page With Bad Extra Byte
NO
P/N: PM0305
7
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential VALUE -10C to 85C -65C to 125 C -0.5V to 3.8V -0.5V to 3.8V -0.5V to 3.8V NOTICE: 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2.Specifications contained within the following tables are subject to change.
CAPACITANCE TA = 25C, f = 1.0 MHz
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance MIN. TYP MAX. 10 16 UNIT pF pF CONDITIONS VIN = 0V VOUT = 0V
INPUT TEST WAVEFORMS AND MEASURESMENT LEVEL
3.0V 1.5V
AC Measurement Level
0V
OUTPUT LOADING
DEVICE UNDER TEST
CL = 30 pF
P/N: PM0305
8
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
DC CHARACTERISTICS = -10C to 85C, VCC = 2.7V ~ 3.6V
SYMBOL IIL PARAMETER Input Load Current Output Leakage Current VCC Standby Current(CMOS) NOTES MIN. 1 TYP MAX. 10 UNITS uA TEST CONDITIONS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VIN = VCC or GND VCC = VCC Max CS = VCC 0.2V
ILO
1
10
uA
ISB1
1
30
60
uA
ISB2
VCC Standby Current(TTL)
1
2
mA
VCC = VCC Max CS = VIH
IDP
VCC Sleep Current VCC Read VCC Program Current VCC Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
1
1
10
uA
CS = VCC 0.2V
ICC1 ICC3
1 1
10 10
30 30
mA mA Program in Progress
ICC4 VIL VIH VOL VOH
1 2 3 -0.5 2.4
10
30 0.4 VCC+0.5 0.45
mA V V V V
Erase in Progress
IOL = 500uA IOH = -100uA
2.4
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.0V, T = 25 These currents are valid for all product C. versions (package and speeds). 2. VIL min. = -1.0V for pulse width < 50ns. VIL min. = -2.0V for pulse width < 20ns. 3. VIH max. = VCC + 1.5V for pulse width < 20ns. If VIH is over the specified maximum value, read operation cannot be guaranteed.
P/N: PM0305
9
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
AC CHARACTERISTICS
SYMBOL fSCLK tCYC tSKH tSKL tR tF tCSA tCSB tCSH tDSU tDH tAA tDOH tPSH tPHO tECY tPCY tSR tWUT PARAMETER Clock Frequency Clock Cycle Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time CS Lead Clock Time CS Lag Clock Time CS High Time SI Setup Time SI Hold Time Acess Time SO Hold Time PROT Setup Time PROT Hold Time Erase Cycle Time Program Cycle Time Status Read After CS Wake Up Time 1 25 25 25 8 3 50 50 100 5 25 5 55 5 Min. 0 100 50 50 10 10 Typ. Max. 11 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms us us Conditions
SERIAL DATA INPUT/OUTPUT TIMING
CS
tCSA tSKH tCYC tSKL tF tCSH tR tCSB
SCLK
tDSU tDH
SI
HIGH IMPEDANCE
BIT 7
tAA
BIT 6
tDOH
BIT 0
SO
BIT 7
BIT 6
BIT 0
HIGH IMPEDANCE
PROT SIGNAL TIMING
CS
tPSH tPHO
PROT
P/N: PM0305
10
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
Revision History
Revision No. 2.4 2.5 2.6 2.7 Description Page Standby mode current changed to 30uA. Flow chart typing error. Add one error byte. Operation conditon changed to 2.7V~3.6V/11MHz and no defect byte is alowed. tDH value is also changed. Change operation temperature from 0~60C to -10~85 C P8;P9 tAA change from 45ns to 55ns @ -10~85C operation P10 Date Nov/20/96 Dec/26/96 Mar/31/98 Sep/25/98
P/N: PM0305
11
REV. 2.7, SEP 14,1998
INDEX
MX25L4004
32-PIN PLASTIC TSOP(I)
ITEM A B C D E F G H I J K L M N
NOTE:
MILLIMETERS 20.0 .20 18.40 .10 8.20 max. .15[Typ.] .80[Typ.] .20 .10 .30 .10 .50[Typ.] .45 max. 0 ~ .20 1.00 .10 1.27 max. .50 0 ~ 5
INCHES .078 .006 .724 .004 .323 max. .006[Typ.] .031[Typ.] .008 .004 .012 .004 .020[Typ.] .018 max. 0 ~ .008 .039 .004 .050 max. .020 .500
K D E F G H I J L M O N C A B
Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition.
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12

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